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bright preliminary BM29F040 m icroelectronics inc. 4 megabit (512k x 8) 5 volt sector erase cmos flash memory a winbond company publication release date: may 1999 - 1 - revision a1 general description the BM29F040 is a 4 megabit, 5.0 volts only flash memory device organized as 512k 8 bits each. the BM29F040 is offered in an industry standard 32-pin package which is backward compatible to 1 megabit and also pin compatible to eeproms. the device is offered in pdip, plcc and tsop packages. the device is designed to be programmed and erased in system with the standard system 5 volt vcc supply. an external 12.0 volts vpp is not required for program and erase operation. the device can also be reprogrammed in standard eprom programmers. the BM29F040 offers access times between 70 to 150 ns. the device has separate chip enable ( ce ), write enable ( we ) and output enable ( oe ) controls to eliminate bus contention. bmi flash memory technology reliably stores memory information even after 100,000 erase and program cycles. the bmi proprietary cell technology enhances the programming speeds and eliminates over erase problems seen in the classical etox ? type of flash cell technologies. the combination of cell technology and internal circuit design techniques give reduced internal electrical fields and this provides improved reliability and endurance. the BM29F040 is entirely pin and command set compatible to the jedec standard 4 megabit eeprom. the commands are written to the command state machine using standard microprocessor write timings. the internal programming and erase algorithms are automatically implemented based on the input commands. the BM29F040 is programmed by executing the program command sequence. this will start the internal automatic program algorithm that times the program pulse width and also verifies the proper cell margin. erase is accomplished by executing the erase command sequence. the internal power switching state machine automatically executes the algorithms and generates the necessary voltages and timings for the erase operation. the program and erase verify is also done internally and proper margin testing is automatically performed. this scheme unburdens the microprocessor or microcontroller from generating the program and erase algorithms by controlling all the necessary timings and voltages. the entire memory is typically erased in 1.5 seconds. no preprogramming is necessary in this technology. the BM29F040 also features a sector erase architecture. it is divided into 8 sectors of 64k bytes each. each sector can be erased individually without affecting the data in other sectors or they can be erased in a random combination of groups. this multiple sector erase capability or full chip erase makes it very flexible to alter the data in BM29F040. to protect the data from accidental program or erase the device also has a sector protect or multiple sector protect function. the device features a single 5 volt power supply for read, program and erase operation. internally generated and well regulated voltages are provided for the program and erase operation. a low vcc detector inhibits write operations during power transitions. the end of program or erase is detected by data polling of dq7 or by the toggle bit feature on dq6. once the program or erase cycle has been successfully completed, the device internally resets to read mode.
bright preliminary BM29F040 m icroelectronics inc. - 2 - features 5.0 v +/- 10% program and erase - minimizes system power consumption - simplifies the system design compatible with jedec standard commands - uses same software commands as eeproms compatible with jedec-standard byte wide pinout - 32 pin plcc/tsop - 32 pin dip automated sector/chip erase algorithms - no programming before erase needed - internal program and erase margin check data polling and toggle bit - useful for detection of program and erase cycle completion sector erase architecture - 8 equal sectors of 64k bytes each - any combination of multiple sector erase - full chip erase sector protection - any number of sectors can be protected from program and erase operation low power consumption typically 100,000 program/erase cycles erase suspend and resume - suspend the sector erase operation to allow a read in another sector low vcc write inhibit < 3.2 volts single cycle reset command product selection guide family part no: -75* -90 -120 -150 maximum access time (ns) 70 90 120 150 ce (e) access time (ns) 70 90 120 150 oe (g) access time (ns) 30 35 50 60 table 1 *this speed is available with vcc = 5v +/- 5% variation
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 3 - revision a1 pin configurations dip top view a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we a17 a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 plcc top view 14 15 16 17 18 19 20 a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o's 1 2 3 4 5 6 gnd a15 a18 we 5 6 7 9 10 11 12 13 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 a12 a16 vcc a17 tsop top view type 1 a11 a9 a8 a13 a14 a17 we vcc a18 a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe a10 ce i/07 i/06 i/05 i/04 i/03 gnd i/02 i/01 i/00 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
bright preliminary BM29F040 m icroelectronics inc. - 4 - flexible sector-erase architecture: 64k bytes per sector individual sector, multiple sector or bulk erase capability. individual or multiple-sector protection is user definable. table 2. sector definition 64k byte sector 70000h-7ffffh 64k byte sector 60000h-6ffffh 64k byte sector 50000h-5ffffh 64k byte sector 40000h-4ffffh 64k byte sector 30000h-3ffffh 64k byte sector 20000h-2ffffh 64k byte sector 10000h-1ffffh 64k byte sector 00000h-0ffffh pin description symbol type name and function a 0 - a 18 i address inputs : for memory addresses. addresses are internally latched during a write cycle. a 9 i address input : when a 9 is at 12 volts the id mode is accessed. during this mode a 0 decodes between the manufacturer and device id s. dq 0 -dq 7 i/o data inputs / outputs : inputs array data on the fourth ce and we cycle during a program command. inputs commands we to the command register when ce and we are active. data is internally latched during the program cycles. outputs are from array and intelligent identifier information. the output pins float to tri-state when the chip is deselected or the outputs are disabled. ce i chip enable : activates the device's control logic, input buffers, decoders and sense amplifiers. ce is active low control; ce high deselects the memory device and reduces power consumption to standby levels. oe i output enable : oe is active low control signal. this pin gates the device ?s outputs through the data buffers during a read cycle. when ce is low and oe is high the outputs are tri-state. we i write enable : controls writes to the command state machine and memory array. we is active low signal. addresses and data are latched during the rising edge of the we pulse. vcc device power supply : main power source to the device. it s value is 5v 10% or 5v 5%. gnd ground : the device ground for the internal circuitry. table 3
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 5 - revision a1 block diagram dq 0 - dq 7 a 0 - a 18 data latch input / output buffers chip enable output enable logic y-mux / sensing array y-decode x-decode a d d r e s s l a t c h state control command register ce we oe vcc gnd vcc detect timer erase voltage generator program voltage generator figure 1 bus operation operation ce oe we a0 a1 a6 a9 i/o auto select manufacturers id (1) l l h l l l v id code auto select device id (1) l l h h l l v id code read l l h a 0 a 1 a 6 a 9 dout standby h x x x x x x high z output disable l h h x x x x high z write l h l a 0 a 1 a 6 a 9 din (2) enable sector protect l v id l x x x v id x verify sector protect (3) l l h l h l v id code table 4 notes: 1. legends: l = v il , h = v ih , x = don't care, v id = +12v. 2. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 6 for command definitions. 3. refer to table 4 for valid din during a write operation. 4. refer to the section on sector protection.
bright preliminary BM29F040 m icroelectronics inc. - 6 - autoselect codes type a 18 a 17 a 16 manufacturer code BM29F040 device code sector protection (1) sector addresses x x x x x x a 0 code (hex) dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 vil vil vih a 1 vil vil vih adh 40h 01h 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 a 6 vil vil vil table 5 product family principles of operation flash memory devices are electrically alterable non-volatile memory products. the BM29F040 augments this feature by not requiring an additional vpp power supply. the 4 megabit flash family uses a command register and internally generated voltages and timing algorithms to make program and erase operations simple. the user need not worry about generating tightly controlled high voltages on board or tying up the microcontroller to generate program and erase algorithms. the command register allows for 100% ttl-level control inputs, and maximum compatibility with the flash memory functions. the device provides standard eprom read, standby and output disable operations. manufacturer identification and device identification data can be accessed through the command register or through the standard eprom 2 a9 2 high voltage access (v id ) for prom programming equipment. a command register and power switching state machine are built inside the device. their purpose is to completely automate the program and erase operation. the command register receives the commands given by the user and internally controls the power switching state machine. read mode the BM29F040 has three control pins and they should all be logically active to obtain valid data at the outputs. chip-enable ( ce ) is the device selection control. output enable ( oe ) is the data input/output control. this pin when high (v ih ) brings the output drivers to the tristate and allows data into the device. data input is then controlled by we . when the oe pin is low (v il ) it enables the output buffers and valid array data becomes available at the output pins. the write enable ( we ) pin has to be high during the read mode. standby mode the BM29F040 has two standby modes: a cmos standby mode ( ce input = vcc +0.5v) when the current consumed is less than 100 m a; and a ttl standby mode ( ce is held at v ih ) when the current consumed is approximately 1 ma. in the standby mode the outputs are in a high impedance state independent of the oe input. if the device is deselected during erasure or programming, the device will draw active current until the erase or programming operation is complete.
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 7 - revision a1 autoselect mode the autoselect mode allows access to the manufacturers and the device code. this mode can be enabled by either taking the address pin a9 to v id (11.5 to 12.5 volts) or by giving the autoselect command sequence as shown in table 5. once the autoselect mode is enabled two identifier bytes can be read on the device outputs by toggling a0 from v il to v ih . byte 0 (a0 = v il ) represents the manufacturers code (adh for bmi). byte 1 (a0 = v ih ) represents the device identifier and this is 40h for the BM29F040. a read command must be written to the command register to return to the read mode after the autoselect mode. write operations the on-chip state machines control the chip erase, sector erase and byte write operations. this frees the system processor to do other tasks. all the programming and erase voltages are generated internally. the write and erase timings and algorithms are also built into the device. the byte write/ sector erase or chip erase command interface provides additional data protection to avoid accidental write or erase. commands are written to the command register using standard microprocessor write timings. the command register recognizes read mode, autoselect mode, chip erase, sector erase (64k bytes per sector) and program commands. the command register does not occupy an addressable memory location. the interface register is a latch used to store the command and address and data information needed to execute the command. command definitions device operations are selected by writing specific address and data sequences into the command register. table 6 defines these command sequences. read/ reset command the read or reset operation is initiated by writing the read/reset command sequence to the command register. processor read cycles retrieve the data from the memory. the device remains enabled for reads until the command register contents are changed. the device will automatically power-up in the read/reset mode. in this case, a command sequence is not needed to read the memory data. this default power up to read mode ensures that no spurious changes of the data can take place during power-up. as shown in this data sheet, the timing parameters and a.c. read waveforms should be referenced. a single cycle reset is also available as shown in table.
bright preliminary BM29F040 m icroelectronics inc. - 8 - table 6. command definitions command sequence bus write cycles first bus write cycle second bus write cycle third bus write cycle fourth bus write cycle fifth bus write cycle sixth bus write cycle required address data address data address data address data address data addres s data read /reset 1 xxxxh f0h read /reset 4 5555h aah 2aaah 55h 5555h f0h ra rd auto select 4 5555h aah 2aaah 55h 5555h 90h 00h adh 01h 40h auto select sector 4 5555h aah 2aaah 55h 5555h 90h sa 00 protect verify x02 01 byte program 4 5555h aah 2aaah 55h 5555h a0h pa pd chip erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h sector erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 30h sector erase suspend 1 xxxxh b0h sector erase resume 1 xxxxh 30h notes: 1. address bit a15, a16, a17 and a18 = x = don t care for all address commands except for program address (pa) and sector address (sa). 2. bus operations are defined in table 4. 3. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched o n the falling edge of we. sa = address of the sector to be erased. the combination of a16, a17 and a18 will uniquely select the sector. 4. rd = data from the selected address location (ra) during read operation. pd = data to be programmed at the selected memory location (pa). data is latched at the falling edge of /we. 5. auto select command can be used to evaluate whether a block is protected or not by using at the fourth address 02h. this is similar to placing a9 to high voltage. auto select command the BM29F040 contains two different procedures for the autoselect mode. one is the traditional prom programmer methodology (by taking address pin a9 to v id ) and the other is by writing the auto select command sequence into the command register. following the third bus cycle write command, a read cycle from address 00h retrieves the bmi manufacturer code adh, and a read cycle at 01h retrieves the device code of 40h. scanning the sector addresses (a16, a17, a18) while (a6, a1, a0) = (0, 1, 0) will produce a logical at device output dq0 for a protected sector. see table 5 for more details.
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 9 - revision a1 to terminate this operation, it is necessary to write the read/ reset command to the command register. byte write or byte program the BM29F040 is programmed one byte at a time. programming is a four bus cycle operation. there are two 2 unlock 2 write cycles which are followed by a program set-up command and data write cycles. addresses are latched on the falling edge of we and data is latched on the rising edge of we . the rising edge of we begins programming. during the execution of the embedded program algorithm the host system is not required to provide any other controls or timings. the device also provides adequate program margin and all the necessary voltages and timings. when completed, the automatic programming will provide the equivalent of the written data on dq7. after a successful programming operation the device returns back to read mode. data polling must be performed at the memory location which is being programmed. figure 3 illustrates the embedded programming algorithm and the waverforms are shown in figures 9 and 10. chip erase chip erase is a six bus cycle operation. there are two "unlock" write cycles. these are followed by writing the 2 setup 2 command. two more 2 unlock 2 write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. BM29F040's technology is immune to overerase and it does not need any internal programming algorithm before erase. this can save erase time in many applications. the automatic chip erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq7 is "1", and which time the device returns back to the read mode. figure 4 illustrates the auto erase algorithm and the erase waveforms are shown in figure 11. sector erase sector erase is a six bus cycle operation. there are two "unlock" write cycles followed by writing the sector erase setup command. two more "unlock" write cycles are then followed by the sector erase confirm command. the sector address is latched on the failing edge of we , and the command data is latched on the rising edge of we . an 80 m s time-out from the rising edge of we of the last sector erase command is initiated. the actual sector erase starts 100 us after the last rising edge of we . multiple sectors can be erased simultaneously. after writing the six bus cycle command for sector erase additional sector address and sector erase command can be inserted within the 80 us time-out period. the timer is reset every time and additional sector erase command is inserted. the sectors can be added to be erased in any random sequence. any command other than the sector erase command or erase suspend command during the time-out period will reset the device to the read mode and ignoring the previous command string. during the execution of the sector erase command, only the erase suspend and erase resume commands are allowed. all other commands will reset the device to the read mode. once the device resets to the read mode due to command error during sector erase, the data in this sector has lost its integrity. the sector should be properly erased again.
bright preliminary BM29F040 m icroelectronics inc. - 10 - sector erase does not require the user to program the sector before erase. when erasing a sector or multiple sectors the data in the unselected sectors remains unchanged. after the sector erase operation is completed the data on dq7 becomes 2 1 2 , and the device returns to the read mode. data polling must be performed at an address within any of the sectors being erased. figure 4 shows the embedded erase algorithm and figure 11 shows the sector erase waveforms. erase suspend and resume the erase suspend command allows the user to interrupt the sector erase function and then read data from the other sectors which were not being erased. this command is not applicable during the chip erase operation or during the program mode. the erase suspend command (b0h) will terminate the sector erase operation and it may require form 0.1 m s to 70 m s to suspend the erase operation and go into the read mode (pseudo read mode). the user must use the toggle bit to determine if the chip has entered the erase suspended read mode, at which time the toggle bit will stop toggling. an address of a sector not being erased must be used to read the toggle bit. the user must keep the information whether the device is in pseudo read mode or read mode. every time an erase suspend command followed by an erase resume command is written the internal counters are reset. the erase suspend command is allowed during the 100 us time out window before the actual sector erase operation starts. the erase resume command will start the erase operation immediately and there is no time out window during erase resume. note that any other command during the time out will reset the device to read mode. to resume the sector erase operation after pseudo read mode the resume command (30h) should be written. the sector erase will start immediately. another erase suspend command can be written after the chip has resumed the erase operation. note that a data "0" can not be programmed back to "1." attempting to do so may give erroneous results or may hang up the device. only an erase operation can change the data from a "0" to "1". the system may also write the autoselect command during the erase suspend mode. this allows the host system to correctly read the autoselect codes during erase suspend since this data is not stored in the memory array. sector protection the BM29F040 has a hardware sector protection. this feature will disable both program and erase operation of the protected sector or group of sectors. the device is shipped with all sectors unprotected. to verify if a sector is protected, the programming equipment must force v id on the address pin a9, and a6 = ce = oe = v il and we = v ih . reading the device at a particular sector address (a16, a17 and a18) and xxx2h will produce 01h at the data outputs for a protected sector. see figure 14 for the ac waveforms and figure 16 for the algorithm. please use the appropriate approved programmer or contact bright for the BM29F040 programmers guide for the specification for protecting individual sectors. sector unprotection the BM29F040 also features a sector unprotect mode, so that a protected sector may be unprotected. all sectors are unprotected at the same time. please use the appropriate approved programmer or contact bright for the BM29F040 programmers guide for the specification to unprotect the sectors.
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 11 - revision a1 it is also possible to determine if a sector is unprotected in the system by writing the autoselect command and a6 is set to v ih . performing a read operation at xxx2h and the sector address (defined by a16, a17 and a18) will produce 00h at the data outputs for an unprotected sector. table 7 sector address table sector a18 a17 a16 address range sa0 0 0 0 00000h - 0ffffh sa1 0 0 1 10000h - 1ffffh sa2 0 1 0 20000h - 2ffffh sa3 0 1 1 30000h - 3ffffh sa4 1 0 0 40000h - 4ffffh sa5 1 0 1 50000h - 5ffffh sa6 1 1 0 60000h - 6ffffh sa7 1 1 1 70000h - 7ffffh data flags dq7 data polling the BM29F040 features data polling to indicate to the host system that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the complement of the data last written to dq7. upon completion of the embedded programming algorithm an attempt to read the device will produce the true data last written to dq7. data polling is valid after the rising edge of the fourth we pulse in the four write pulse sequence. during the embedded erase algorithm, dq7 will be "0" until the erase operation is completed. upon completion of erase the data at dq7 is "1". for sector erase, the data polling is valid after the last rising edge of the sector erase we pulse. for chip erase, the data polling is valid after the last rising edge of the sixth chip erase we pulse. data polling must be performed at a sector address within any of the sectors being erased and not a protected sector. once the embedded operation is close to being completed, the BM29F040 data pins (dq7) may change asynchronously while the oe pin is asserted low. this means that the device is driving status information on dq7 at one time and bytes of valid data at other times. depending on when the system samples the dq7 output it may read the status or it may read the valid data. see figure 12 for the data polling timing diagram. dq6 toggle bit the BM29F040 also features the "toggle bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read data from the device will result in dq6 toggling between "1" and "0". once the embedded program or erase algorithm cycle is completed, dq6 will stop toggling and valid data will be read on successive attempts. during programming the toggle bit is valid after the rising edge of the fourth we pulse in
bright preliminary BM29F040 m icroelectronics inc. - 12 - the four write pulse sequence. during chip and sector erase, the toggle bit is valid after the rising edge of the sixth we pulse in the six write pulse sequence. in programming, if the sector being written to is protected, the toggle bit may toggle for about 2 m s and then will stop toggling without the data being changed. during erase the device will erase all the sectors except the sector being protected. if all the sectors are protected the chip will toggle the toggle bit for about 2 m s and then drop back to read mode without changing the data. either ce or oe toggling will cause the dq6 to toggle. the toggle bit is valid in the time out period during sector erase. see figure 13 for the toggle bit timing diagrams. dq5 exceeded the timing limits dq5 indicates if the program or erase time has exceeded the specified timing limits. under these conditions dq5 will produce a "1". this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions. the oe and we pins will control the output disable function as shown in table 4. if this failure condition occurs during the sector erase operation, it indicates that the particular sector is bad and may not be reused. the other sectors are still functioning properly and can be used. the device must be reset to use the other good sectors. to reset the device, write the reset command sequence to the device. this will allow the system to use the other active sectors in the device. if this failure condition occurs during chip erase, it indicates that the entire chip is bad or many sectors are bad. if this condition occurs during byte write it indicates that the sector containing this byte is bad. this failure condition can also occur if the user tries to program a non-blank location without erasing. in this case the device locks out and never completes the operation. please note that this is not a device failure. dq3 sector erase timer after the completion of the sector erase command sequence the sector erase time-out begins. dq3 will remain low until the time-out is complete. data polling and the toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, dq3 may be used to determine if the sector erase timer window is still open. if dq3 is "1" the internally controlled erase cycle has begun. if dq3 is 2 0 2 the device will accept additional sector erase commands. to ensure that the command has been accepted, the user should check the status of dq3 prior to and following each sector erase command. if dq3 is "1" on the second status check, the command may not be accepted. once the internal erase cycle begins the device will not accept any other command until the internal erase cycle is completed. the BM29F040 is designed to offer protection against accidental programming or erasure. during power-up the device automatically resets to the read mode. the multi-bus command sequences also provide data protection for accidental write. the device also provides additional features to prevent inadvertent write operations during power-up and power-down transitions or system noise.
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 13 - revision a1 dq2 toggle bit ii the BM29F040 also features the "toggle bit ii" as a method to indicate to the host system whether a specific sector is actively erasing or whether the sector is erase-suspended. the toggle bit ii is valid after the rising edge of the final we pulse in the command sequence. dq2 toggles when the host system reads addresses within a sector that have been selected for erase. the system may use oe or we to control the read cycles. but, dq2 can not distinguish between a sector erasing or erase-suspended. however, toggle bit dq6 can be used to determine if a sector is actively erasing or erase-suspended. as a result, both toggle bits are required for the host system to determine the current mode information. refer to table 7 for a further comparison of dq6 and dq2. whenever the host system begins to read the erase status using the toggle bits, they must be read at least twice in a row. typically, the system would store the first value and compare it to the second. if the bits are still toggling, the system should also check dq5(see the dq5 description). if dq5 is high, the system should re-check the toggle bits since toggling may have just finished. if the toggle bits have stopped toggling, the device has successfully completed the erase. if the toggle bits are still toggling, the device has not successfully completed the erase operation and the host should issue a reset command to the device before continuing. if dq5 is low, the host system should continue to monitor the toggle bits and dq5 or issue an erase suspend command if performing a single or multiple sector erase command. write operation status status dq7 dq6 dq5 dq3 dq2 standard auto-programming ____ dq7 toggle 0 n/a no toggle auto-erase 0 toggle 0 1 toggle erase suspend reading an erase suspended sector 1 no toggle 0 n/a toggle reading a non-erase suspended sector data data data data data auto-programming erase suspend ____ dq7 toggle 0 n/a n/a exceeded auto-programming ____ dq7 toggle 1 1 reserved for time limits auto-erasing 0 toggle 1 1 future use table 8. hardware sequence flags low vcc write inhibit during vcc power-up or power-down, a write cycle is inhibited for vcc values of less than 3.2 volts (3.8 volts typical). if vcc < vlko (vlko = lock out voltage) the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. if a write command is given during vcc < vlko, the writes will be ignored. it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when vcc > vlko. write pulse glitch protection
bright preliminary BM29F040 m icroelectronics inc. - 14 - noise pulses of less than 5 ns on oe , we or ce will not initiate a write cycle. power-up wtire inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands at the rising edge of we . the internal state machine is automatically reset to the read mode on power-up. logical inhibit writing is inhibited by holding any one of the control pins to oe = v il , we = v ih or ce = v ih . to initiate a write cycle, ce and we must be logical "0" and oe must be logical "1" . sector protect sectors of the BM29F040 may be hardware protected by the user. the protection circuitry will disable both program and erase functions for the protected sectors. the program and erase commands will be ignored if given to the protected sectors. the chip erase command will also not erase the protected sectors. parallel device erasure the BM29F040 is a fully self timed device. this makes it feasible to erase or program many devices in parallel. program command sequence (address/data) 5555h/ aah 2aaah/ 55h 5555h/ a0h program add./program data fourth write cycle third write cycle second write cycle first write cycle figure: 3a embedded programming flow chart start write program command sequence (see fig. 3a) data poll device verify byte ? byte write completed yes no figure: 3b note: see data polling algorithm in figure 10 and 11.
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 15 - revision a1 embedded erase algorithm start write program command sequence (see below) data poll device data = ffh ? erasure completed yes no figure 3. embedded programming algorithm note: see data polling algorithm in figure 5 chip erase command sequence (address/data) 5555h/ aah 2aaah/ 55h 5555h/ 80h fourth write cycle third write cycle second write cycle first write cycle 2aaah/ 55h 5555h/ aah 5555h/ 10h fifth write cycle sixth write cycle individual sector/multiple sector erase command sequence (address/data) 5555h/ aah 2aaah/ 55h 5555h/ 80h fourth write cycle third write cycle second write cycle first write cycle 2aaah/ 55h 5555h/ aah sector address/ 30h fifth write cycle sixth write cycle sector address/ 30h sector address/ 30h additional sector erase commands are optional figure 4. automated erase flow chart and sequence
bright preliminary BM29F040 m icroelectronics inc. - 16 - data polling algorithm start no yes ? dq 7 = data dq 5 =1 ? dq 7 = data ? no yes fail pass yes no note 1 note: dq7 is rechecked even if dq5 = "1" because dq7 may change simultaneously with dq5. toggle bit algorithm start no yes ? dq 6 = toggle dq 5 =1 ? dq 6 = toggle ? no yes fail pass yes no note 2 note: dq6 is rechecked even if dq5 = "1" because dq6 may stop toggling at the same time as dq5 is changed to "1". figure 5. data polling and toggle bit algorithm absolute maximum ratings: storage temperature -65 c to +125 c operating temperature (note 1) during read -55 c to +125 c duri ng program/erase -55 c to +125 c temperature under bias (with power applied) -55 c to +125 c voltages with respect to gnd. all pins except a9 (note 2, 3) -2v to +7v vcc (note 2) -2v to +7v a9 (note 3) -2v to +14v output short circuit current (note 4) 200ma operating ranges: commercial (c) devices temperature range 0 c to +70 c vcc supply voltage during 4.5v to 5.5v or all operations 4.75v to 5.25v industrial (i) devices temperature range -40 c to +85 c vcc supply voltage during 4.5v to 5.5v all operations notes : 1. the datasheet defines the operation at specific temperature ranges. 2. minimum dc voltage on input / output pins is -0.5v. during voltage transitions, inputs can undershoot to -2 volts for periods of up to 20 ns. the maximum dc voltage on these pins is vcc +0.5v. during transitions, inputs may overshoot to vcc +2.0v for periods < 20 ns. 3. maximum dc voltage on a9 may overshoot to 14.0v for periods < 20 ns. 4. outputs may be shorted for no more than one second. only one/output can be shorted at a time. *notice: stresses above those listed under "absolute maximum ratingsz" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 17 - revision a1 maximum overshoot maximum negative overshoot -2.0 v -0.5 v +0.8 v 20 ns 20 ns 20 ns maximum negative overshoot waveform vcc + 2.0 v vcc + 0.5 v 2.0 v maximum positive overshoot waveform 20 ns 20 ns 20 ns figure 6. maximum overshoot waveforms dc characteristics symbo l parameter min max unit test conditions vil input low level -0.5 0.8 v vih input high level 2.0 vcc + 0.5 v vol output low voltage 0.45 v lol = 12ma vcc = vcc min. voh output high voltage 2.4 v loh = -2.5ma vcc = vcc min. voh 2 output high voltage vcc - 0.4 v lohl = -100ua vcc = vcc min. l li input load current +/- 1.0 ua vin = vcc or gnd vcc = vcc max. l lo output leakage current +/- 10 ua vout = vcc or gnd vcc = vcc max. l os output short circuit current 100 ma vout = 0.5v vcc = vcc max. l sb 1 vcc standby current (cmos) 4 100 ua ce = vcc +/- 0.5v vcc = vcc max. l sb 2 vcc standby current (ttl) 4 1.0 ma ce = vih vcc = vcc max. l cc 1 vcc active current read 1,3 40 ma ce = vil, f = 6mhz, oe = vih l cc 2 vcc active current program or 2 60 ma ce = vil, oe = vih v id a9 intelligent identifier volatge 11.5 12.5 v l id a9 intelligent identifier current 50 ua a9 = vid table 9 notes: 1. all currents are in rms unless otherwise noted. typical values are vcc = +5.0v, t = 25 c. 2. these parameters are sampled but not 100% tested. 3. automatic power saving reduces the iccr to 1 ma. 4. cmos inputs are vcc +0.5v. ttl inputs are either v il or v ih .
bright preliminary BM29F040 m icroelectronics inc. - 18 - capacitance: t a = 25 c, f = 1 mhz (2) symbol parameter conditiontion typical max unit cin input capacitance vin = 0v 6 8 pf cout output capacitance vout = 0v 10 12 pf ac testing input/output waveform ac test inputs are driven at voh ( 2.4v vttl) for a logic "1" and vol ( 0.4v vttl) for a logic "0". input timing measurement begins at vih ( 2.0v vttl) for an input "1" and vil ( 0.8v vttl) fir an input "0". output timing measurement ends ar 2.0v for an output "1" and 0.8v for an output "0". input rise and fall times (10% to 90%) < 10ns. 2.4 0.45 input 2.0 0.8 test points 2.0 0.8 output ac testing load circuit device under test c l r l r l 6.2k 2.7k c = 100 pf c includes jig capacitance the diodes are 1n3064 or wequivalent. l l figure 7. a.c.testing load and waveforms
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 19 - revision a1 ac characteristics - read only operations (1) symbol (4) description -75 -90 -120 -150 units jedec standard tavav trc read cycle time 70 90 120 150 ns tavqv tacc address to output delay 70 90 120 150 ns telqv tce ce low to output delay (2) 70 90 120 150 ns tglqv toe oe low to output delay 30 35 50 55 ns telqx tlz ce low to output low z (3) 0 0 0 0 ns tehqz thz ce high to output high z 20 20 30 35 ns tglqx tolz oe low to output low z 0 0 0 0 ns tghqz tdf oe high to output high z (3) 20 20 30 35 ns taxqx toh output hold from address, ce or oe , whichever is first (1) 0 0 0 0 ns table 11 notes: 1. see a.c. input/output reference waveforms for timing measurements. 2. oe may be delayed up to tce-toe after the falling edge of ce without impact on tce. 3. sampled, not 100% tested. 4. see a.c. input/output reference waveforms and a.c. testing load circuits for testing characteristics. data (d/q) ghqz t t glqv valid output t axqx high z t avqv high z vih vil oe (g) ce (e) address valid vih vil addresses vih vil vil vih t elqv vil vih we (w) t elqx t glqx 5.0 v vcc gnd ehqz t t avav vcc power- up standby device & address select. outputs enabled data valid standby vcc power- down figure 8. a.c.waveforms for read operations
bright preliminary BM29F040 m icroelectronics inc. - 20 - ac characteristics - for we controlled write operation symbol description -75 -90 -120 -150 units jedec standard tavav twc write cycle time (4) 70 90 120 150 ns telwl tcs ce setup 0 0 0 0 ns tavwl tas address setup time 0 0 0 0 ns tdvwh tds data setup time 30 45 50 55 ns twlwh tdh data hold time 0 0 0 0 ns twheh tch ce hold time 0 0 0 0 ns twlax tah address hold time 45 45 50 50 ns twlwh twp write pulase width 35 45 50 50 ns twhwl twph we pulse width high 20 20 20 25 ns toes output enable setup time 0 0 0 0 ns toeh output enable read (4) 0 0 0 0 ns hold time toggle and data polling 10 10 10 10 ns tghwl tghwl read recover time before write 0 0 0 0 ns twhwh1 twhwh1 programming operation 16 16 16 16 us twhwh2 twhwh2 erase operation (min.) (1) typ 1.5 1.5 1.5 1.5 sec max 30 30 30 30 sec tvcs vcc setup time (4) 50 50 50 50 us tvlht voltage transition time (2,4) 4 4 4 4 us twpp1 write pulse width (2) 100 100 100 100 us twpp2 write pulse width (2) 10 10 10 10 ms tcesp ce setup time to we active (3,4) 4 4 4 4 us toesp 4 4 4 4 us table 12 notes: 1. the erase operation does not need programming time. 2. these timings are for sector protect/unprotect operation. 3. this timing is only for sector unprotect. 4. not 100% tested.
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 21 - revision a1 switching waveforms gnd addresses (a) data (d/q) vcc oe (g) 5.0 v we (w) vih vil vil vih ce (e) vih vil vil vih vih vil t w c t as t t wph t whwh1 t wp t ds high z 5555h pa pa a0h pd dq7 dout ah t ghwl dh t t cs data polling t rc t ce t oe t df t oh figure 9. a.c.waveforms for program operations ( we controlled writes) notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at the byte address. 3. dq7 is the output of the complement of the data written tot he device. 4. dout is the output of the data written to the device. 5. figure indicates the last two bus cycles of four bus cycle sequence.
bright preliminary BM29F040 m icroelectronics inc. - 22 - ac characteristics - for ce controlled write operation symbol description -75 -90 -120 -150 units jedec standard tavav twc write cycle time (note 4) 70 90 120 150 ns twlel tws we setup time 0 0 0 0 ns tavel tas address setup time 0 0 0 0 ns tdveh tds data setup time 30 45 50 50 ns tehdx tdh data hold time 0 0 0 0 ns tehwh twh we hold time 0 0 0 0 ns twlax tah address hold time 45 45 50 50 ns teleh tcp ce pulse width 35 45 50 50 ns tehel tcph ce pulse width high 20 20 20 25 ns toes output enable setup time 0 0 0 0 ns toeh output enable read (note 4) 0 0 0 0 ns hold time toggle and data polling 10 10 10 10 ns tghel tghel read recover time before write 0 0 0 0 ns twhwh1 twhwh1 programming operation 16 16 16 16 us twhwh2 twhwh2 erase operation (1) typ 1.5 1.5 1.5 1.5 sec max 30 30 30 30 sec tvcs vcc setup time (note 4) 50 50 50 50 m s table 13 notes: 1. the erase operation does not need programming time. 2. these timings are for sector protect/unprotect operation. 3. this timing is only for sector unprotect. 3. not 100% tested.
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 23 - revision a1 switching waveforms addresses (a) vcc data (d/q) oe (g) 5.0 v gnd we (w) vih vil vil vih ce (e) vih vil vil vih vih vil t wc t as t t cph t whwh1 t cp t ds high z 5555h pa pa a0h pd dq7 dout ah t ghel dh t t ws data polling t rc t ce t oe t df t oh figure 10.a.c.waveforms for program operations ( ce controlled writes) notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at the byte address. 3. dq7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. switching waveforms addresses (a) vcc data (d/q) oe (g) 5.0 v gnd we (w) vih vil vil vih ce (e) vih vil vil vih vih vil t as t wph t wp t ds high z 5555h aah t ah t ghwl dh t t cs 5555h 5555h 2aaah 2aaah sa 55h 80h aah 55h 30h for sector erase 10h for chip erase t vcs figure 11. a.c. waveforms for chip/sector erase operations note: sa is the sector address for sector erase or 5555h for chip erase.
bright preliminary BM29F040 m icroelectronics inc. - 24 - switching waveforms t oe high z vih vil oe (g) ce (e) vih vil vil vih vil vih t whwh1 or 2 data (d/q) t t ce data out data out data in t df t oh we (w) t ch t oeh figure 12. ac waveforms for data polling during embedded algorithm operations vih vil oe (g) ce (e) vih vil vil vih vil vih we (w) dq6 data in oeh t oh t oh t figure 13. ac waveforms for toggle bit during embedded algorithm operations operating
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 25 - revision a1 ordering information part no. access time ( n s) power supply current max. ( m a) package cycling ( min ) temperature range 29f040-90nc 29f040-12nc 29f040-90ac 29f040-12ac 29f040-90tc 29f040-12tc 29f040-90ni 29f040-12ni 29f040-90ai 29f040-12ai 29f040-90ti 29f040-12ti 90 120 90 120 90 120 90 120 90 120 90 120 60 60 60 60 60 60 60 60 60 60 60 60 32 pdip 32 pdip 32 plcc 32 plcc 32 tsop 32 tsop 32 pdip 32 pdip 32 plcc 32 plcc 32 tsop 32 tsop 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 10,000 0 c - 70 c 0 c - 70 c 0 c - 70 c 0 c - 70 c 0 c - 70 c 0 c - 70 c -40 c - 85 c -40 c - 85 c -40 c - 85 c -40 c - 85 c -40 c - 85 c -40 c - 85 c notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. typical cycling is 100,000 program and erase cycles.
bright preliminary BM29F040 m icroelectronics inc. - 26 - appendix a: compatibility to amd's amd29f040b the device is fully functional compatible to the amd29f040b except during the command addresses subset mode. in the amd device, commands do not require a unique address pattern for bits a15, a14, a13, a12 or a11 (eg.x555h or x2aah instead of 5555h and 2aaah). that is, the BM29F040 requires specifically a14,a13,a12 and a11 to be forced during the command sequence in addition to a10 through a0. note specifically that the BM29F040 does not require address a15 along with a18, a17 and a16 to be forced during the command sequence. amd's reduced address requirement makes their device slightly easier to inadvertently create a command and cause some program error or malfunction. the advantage of reducing the address is to simplify the hardware interface in systems where control signals are limited in number. the 29f040b reduces the interface requirement by 4 signals -- from 15 to 11 address control pins. however if the full command address is supplied (i.e. 2aaah and 5555h) by the host system, there will be no incompatibility using either device.
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 27 - revision a1 package dimensions 32-pin p-dip 1.dimensions d max. & s include mold flash or tie bar burrs. 2.dimension e1 does not include interlead flash. 3.dimensions d & e1 include mold mismatch and are determined at the mold parting line. 6.general appearance spec. should be based on final visual inspection spec. . 1.37 1.22 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.555 0.550 0.545 14.10 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.650 1.660 41.91 42.16 0 15 0.085 2.16 0.650 0.630 16.00 16.51 protrusion/intrusion. 4.dimension b1 does not include dambar 5.controlling dimension: inches 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 32 1 16 17 32-pin plcc notes: l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusion. 3. controlling dimension: inches 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.9 5 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.49 0 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.51 0 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 q q
bright preliminary BM29F040 m icroelectronics inc. - 28 - package dimensions, continued 32-pin tsop a a a 2 1 l l 1 y c e h d d b e m 0.10(0.004) min. nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d note: controlling dimension: millimeters dimension in inches 0.047 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.005 0.006 0.007 0.720 0.724 0.728 0.311 0.315 0.319 0.780 0.787 0.795 0.020 0.016 0.020 0.024 0.031 0.000 0.004 1 3 5 0.002 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.12 18.30 7.90 19.80 0.40 0.00 1 0.20 0.23 0.15 0.17 18.40 18.50 8.00 8.10 20.00 20.20 0.50 0.50 0.60 0.80 0.10 3 5 dimension in mm __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ 0 0
bright preliminary BM29F040 m icroelectronics inc. a winbond company publication release date: may 1999 - 29 - revision a1 version history version date page description a1 may. 1999 - initial issued headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5796096 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics corporation america 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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